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Lead Partner Pulls Out of India Fab Plan

LONDON--After years of inactivity the Indian government|s long-running project to build two wafer fabs in the sub-continent appears to be in jeopardy, at least on one front.

Local cement and infrastructure company Jaiprakash Associates ? which was the anchor partner in a consortium with IBM and Tower Semiconductor Ltd. to build a wafer fab in Greater Noida in Uttar Pradesh ? has pulled out of the project, according to local reports.

"JP Associates has withdrawn its proposal of semiconductor plant. They have said that it is not commercially viable to set up this plant at present," Aruna Sharma, secretary of the DeitY (Department of Electronics and IT) of the ministry of communications & information technology, government of India told reporters on the sidelines of a Qualcomm event in New Delhi.

Estimates of the spend on the fab vary from 263 billion rupees (about $4 billion) up to 340 billion rupees (about $5 billion) but are somewhat moot as the premise of the projects was that the government would provide funding to subsidize the consortium|s plans. Jaypakash Associates was reported to have high levels of endebtedness.

A spokesperson for Tower Semiconductor Ltd. (Migdal Haemek, Israel) confirmed JP|s withdrawal in a email response to EE Times Europe.

"Indeed JP has withdrawn their part of out consortium. They had the role of investing money in this project. At this point, we are looking for other investors who may have interest in joining this deal," the spokesperson said. "Nevertheless, [you] need to remember that this deal was never part of our business plan, nor in any of our analysts| models."

The slowness of the Indian government, its lack of ability to raise funds, seem to have blighted both wafer fabs.

Jaiprakash Associates and Hindustan Semiconductor Manufacturing Co. (HSMC) were the two consortia approved by government of India to construct wafer fabs back in 2012 (see Tower aims to build 300-mm water fab in India). The Indian government|s thinking was that its negative balance of trade in chips needed to be addressed and it was not sufficient to only try and compensate for that in electronic systems-level activity and software writing.

According to the local reports the JP wafer fab was expected to cost about $4 billion in total and be capable of running 300mm-diameter wafers and run 40,000 wafer starts per month in an advanced CMOS. The plan was to have Tower run the wafer fab as a whole and for IBM to provide CMOS manufacturing processes. The fab would start on 90, 65 and 45nm CMOS nodes before moving on to 28nm CMOS and a 22nm node, still behind today|s leading edge in chip manufacturing, but potentially useful for applications in the Internet of Things

Meanwhile the Hindustan Semiconductor Manufacturing Co. (HSMC), which is linked to STMicroelectronics and Silterra, Malaysia is still expected to move from 90nm down to 28nm and 20nm at a proposed location in Prantij, near Gandhinagar, Gujarat at cost of about 253 billion rupees (about $3.8 billion).  

However, the HSMC project has received the boost of reported support from Lisu Su, CEO of Advanced Micro Devices Inc.. Local reports said that Su had met with Ravi Shankar Prasad, Indian telecom minister, and discussed matters linked to semiconductor policy and its HMSC fab proposal. According to the reports, AMD wants to help transform India into an electronics manufacturing hub.

A third plan to foster a wafer fab in India comes from Cricket Semiconductor LLC, which wants to create an analog and power pure-play foundry near Indore in Madhya Pradesh. This plan came to light in 2015 but still requires details on funding, technology and customers.

This article was originally published by EE Times Europe.

? Peter Clarke covers business news and analog for EE Times Europe.

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