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EnSilica, Micrium Partners on RTOS/MCU Integration

EnSilica and Micrium have partnered to port Micrium¡¯s µC/OS-III RTOS to EnSilica¡¯s family of eSi-RISC processor cores, effective immediately. In addition, Micrium¡¯s range of communication software, including its USB host/USB device and TCP/IP networking protocol stack, has been ported to EnSilica¡¯s eSi-RISC.

Micrium¡¯s µC/OS-III is a pre-emptive and deterministic multi-tasking RTOS with optional round-robin scheduling. It is highly scalable, capable of supporting unlimited application tasks and kernel objects, and also highly portable, being delivered with complete source code and in-depth documentation. Furthermore, it is extremely resource efficient as the kernel|s memory footprint can be scaled down to contain only the features required for the application, typically 6¨C24 KBytes of code space and 1 KByte of data space. Available extensions provide memory protection, greater application stability, safety, memory and time management, enabling cost-effective certification of complex systems. µC/OS-III is used extensively in safety-critical and risk-averse applications being pre-certified to avionics (DO-178B Level E up to Level A), industrial control (IEC 61508 Safety Integrity Level 1 up to Level 3) and medical (ISO 62304 Class A up to Class C [FDA 510(k)]) standards requirements.

EnSilica¡¯s eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scale across a wide range of applications and uniquely support both 16-bit and 32-bit configurations. The cores have been extensively silicon proven in a variety of ASIC technologies down to 28nm. The eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSi-3250 32-bit processor, eSi-3250sfp incorporating a single precision floating point processor, eSi-3260 32-bit processor with SIMD DSP extensions and eSi-32X0MP 32-bit scalable, asymmetric multicore processor. The processor cores also benefit from a configurable memory architecture and configurable cache options.

This article was originally published by EE Times Europe .

¡ªJulien Happich is editor in chief of for EE Times Europe.


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